Program Description
This program is designed to build industry-ready VLSI professionals by equipping learners with a strong foundation in semiconductor design principles and practical skills across the complete chip development cycle. Through a blend of live sessions, hands-on labs, and real-world projects, participants will learn CMOS logic design, Verilog coding, RTL design, synthesis, timing analysis, floorplanning, verification, and advanced techniques like FinFET, low-power design, and hardware security. By the end of the course, learners will be ready to step into high-demand roles such as VLSI Design Engineer, Verification Engineer, or ASIC Engineer, and contribute to the rapidly growing semiconductor industry.
Key Highlights
Gain a strong foundation in VLSI design principles, tools, and workflows.
Be able to design, verify, and implement digital circuits and chips from concept to sign-off.
Build hands-on experience with EDA tools, Verilog, RTL design, synthesis, timing analysis, and verification.
Confidently apply for roles such as VLSI Design Engineer, RTL Engineer, Verification Engineer, or ASIC Engineer in the semiconductor industry.
Showcase your capabilities through a capstone project portfolio that demonstrates industry-relevant skills to potential employers.
Learning Format
Online
Duration
20 Weeks
Certified by
IITM Pravartak Technologies Foundation
Technology Innovation Hub (TIH) of IIT Madras
and
Physics Wallah
Program Fee
₹60,000/- + GST
Downloads
Program Brochure
Education Qualification
1. Graduates (10+2+4) in ECE, EE or related streams
2. Fresh Graduates with strong digital-logic background
3. Completed 1st year of Engineering - targeting chip-design role
Suggested Prerequisites
1. Basic programming in C/Python
2. Strong digital literacy
Lead Faculty
Dr. Uma Varadarajan
Dr. Uma Varadarajan brings over 15 years of specialised expertise in VLSI design, verification, and research, blending strong academic rigour with hands-on execution of advanced projects. As a Faculty at IITM Pravartak, she leads government-funded R&D initiatives in formal verification and next-gen VLSI architectures, ensuring that learners gain exposure to industry-grade methodologies and real-world challenges.Her work spans VLSI front-end design, FPGA prototyping, UVM-based verification, low-power circuit design, cache coherence protocols, and formal verification flows. She has also contributed to security-focused hardware research (PUF-based cyphers) and adaptive memory architectures, strengthening her reputation in both academia and applied R&D. With over 14 publications in SCI/Scopus-indexed journals and international conferences, and the successful supervision of 25+ theses in VLSI and embedded systems, Dr. Uma has consistently advanced the frontiers of chip design and verification. Her unique blend of research leadership and technical depth positions her as a valuable mentor for students aiming to build careers in semiconductor design, FPGA systems, and hardware security.
