The course starts with understanding IC technology advantages, historical timelines, and the process of crafting Integrated Chips from Silica Sand. It covers MOS transistor design complexities, power dissipation types, low-power design techniques, and CMOS logic gate design insights. Participants then focus on circuit schematics/layouts, stick diagrams, Electric VLSI EDA tool usage, and simulation integration with LTspice for analog circuit design. The course also delves into CMOS logic circuit schematic and layout design, covering Design Rule Checking (DRC), simulation, and verification through LTspice for digital circuits. Specific topics include designing PMOS, NMOS, CMOS inverters, amplifiers, oscillators, AND, OR, XOR gates, and half adder circuits for practical verification.
Course Objectives
Online
3 units
IITM Pravartak Technologies Foundation
Technology Innovation Hub (TIH) of IIT Madras
and
L&T EduTech
Rs. 1900/- Inclusive of Tax
Students pursuing diploma/UG/PG Programs in Electrical/Electronics Engineering Department, Computer Engineering Department, or related fields interested in CMOS chip design, simulation, and EDA tool applications. .
Basic understanding of electronics and semiconductor devices, Prior knowledge of analog and digital circuit design principles.
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Dr. P. Rangarajan
Subject Matter Expert, L&T EduTech.
Dr. P. Rangarajan is a Subject Matter Expert in Electrical Engineering. He obtained his doctorate from Anna University in 2004, specializing in VLSI & Signal Processing. He earned his M.E. degree in Power Electronics from Guindy College of Engineering in 1996 and his B.E. degree in Electrical and Electronics Engineering from Coimbatore Institute of Technology in 1990. He has a total of 33 years of work experience. He has published 80 papers in international journals and holds four patents. He is also a recognized supervisor at Anna University, where he has guided nineteen Ph.D. scholars to completion. Additionally, he has executed projects funded by AICTE and DST. He received the CTS Best Faculty Award in 2014.
Introduction to IC Technology, Making of Integrated Chips from Silica Sand, Basics of MOS Transistor, Non-Ideal MOS Transistor Characteristics, Basics of CMOS Inverter, Dynamic Power Dissipation in CMOS Inverter, Static Power Dissipation in CMOS Inverter, Low-Power Design Techniques, CMOS Logic Circuits.
Basics Stick Diagram and layout Design Rules for CMOS Design, Introduction to Electric VLSI EDA Tool Installation and its features, Design of Schematic, Layout and Simulation of PMOS Transistor Current -voltage Characteristics Using Electric VLSI EDA Tool, Design of Schematic, Layout and Simulation of NMOS Transistor Current -voltage Characteristics Using Electric VLSI EDA Tool, Design of Schematic and Simulation of CMOS Inverter Using Electric VLSI EDA Tool, Design of Layout and Simulation of CMOS Inverter Using Electric VLSI EDA Tool, Design of Schematic and Simulation of Common Source Amplifier Using Electric VLSI EDA Tool, Design of Layout and Simulation of Common Source Amplifier Using Electric VLSI EDA Tool, Design of Schematic and Simulation of Common Drain Amplifier Using Electric VLSI EDA Tool, Design of Layout and Simulation of Common Drain Amplifier Using Electric VLSI EDA Tool, Design of Schematic and Simulation of Three Stage Oscillator Using Electric VLSI EDA Tool, Design of Layout and Simulation of Three Stage Oscillator Using Electric VLSI EDA Tool.
Design of Schematic and Simulation of CMOS NAND Gate Using Electric VLSI EDA Tool, Design of Layout and Simulation of CMOS NAND Gate Using Electric VLSI EDA Tool, Design of Schematic and Simulation of CMOS AND Gate Using Electric VLSI EDA Tool, Design of Layout and Simulation of CMOS AND Gate Using Electric VLSI EDA Tool, Design of Schematic and Simulation of NOR Gate Using Electric VLSI EDA Tool, Design of Layout and Simulation of NOR Gate Using Electric VLSI EDA Tool, Design of Schematic and Simulation of OR Gate Using Electric VLSI EDA Tool, Design of Layout and Simulation of OR Gate Using Electric VLSI EDA Tool, Design of Schematic and Simulation of XOR Gate Using Electric VLSI EDA Tool, Design of Layout and Simulation of XOR Gate Using Electric VLSI EDA Tool, Design of Schematic and Simulation of Half Adder Using Electric VLSI EDA Tool, Design of Layout and Simulation of Half Adder Using Electric VLSI EDA Tool